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ASAHI KASEI
[AK4584]
AK4584
24Bit 96kHz Audio CODEC with DIT/DIR
ST*@*@--v
AK4584I 24rbg*A 96kHzOER*[fB"OVXeOEuI**"\ CODECA**B ADCEI*Ch 24bit _Ci~bNOE"WZAOE*eG"n"Xg *Ef...Arbg*uZ(R)*I--p*A DACEI*VSJ"-IAho "Xg *E}rbg*uZ(R)*I--p*A*XE*L_Ci~bNOE"WAE'a`NaeSOmCYZAOEAU**B U1/2*A AK4584I 24rbg*A 192kHzE`I1/2fBW^I*[fBIg"X~b^ (DIT)AEfBW^ I*[fBIOEV*[o (DIR)"a` *A AC-3/MPEG"TMI Non-PCMf*[^XgS*[Z(c)"(R)OEY*oU**B fBW^I*[fBI*o--II DC*o--IAEfBW^"u--I`I`AU**BAK4584I"u--I PGA"a` A Ae*A MD, DVD-R, CD-R--p"rE*A"KA**B
*AC-3I Dolby LaboratoriesI"o^**WA**B "A*@*@'*
1. 24bit 2ch ADC * fs: max 96kHz * Single-end Input * S/(N+D): 90dB * Dynamic Range, S/N: 100dB * Digital HPF for offset cancellation * Input PGA with +18dB gain & 0.5dB step * Input DATT with -72dB ATT * I/F format: MSB justified or I2S 2. 24bit 2ch DAC * fs: max 192kHz * 24bit 8 times Digital Filter - Ripple: 0.005dB, Attenuation: 75dB * Single-end Output * S/(N+D): 94dB * Dynamic Range, S/N: 104dB * De-emphasis for 32kHz, 44.1kHz, 48kHz sampling * Digital Attenuator with soft-transition * Soft Mute * Zero Detect Function * I/F format: MSB justified, LSB justified or I2S 3. 3 Outputs 24 bit 192kHz DIT * 3-Channel Transmission Outputs (2 Through outputs & DIT Output) * 40 Bits Channel Status Buffer
MS0118-J-01 -1-
2001/11
ASAHI KASEI
[AK4584]
4. 4 Inputs 24bit 192kHz DIR * Supports AES3, IEC60958, S/PDIF, EIAJ CP1201 * Low Jitter Analog PLL * PLL Lock Range: 32k 192kHz * Clock Source: PLL or X'tal * 4 Channels Receiver Inputs * Detect Function - Non-PCM Bit Stream Detection - DTS-CD Bit Stream Detection - Validity Flag Detection - Sampling Frequency Detection - Unlock & Parity Error Detection * 40 bits Channel Status Buffer * Burst Preamble bit Pc, Pd Buffer for Non-PCM bit Stream 5. Support External Audio Clock Input * Master Clock Input - 256fs, 384fs, 512fs, 768fs (fs = 44.1kHz 48kHz) - 256fs, 384fs (fs = 88.2kHz 96kHz) - 128fs, 192fs (fs = 176.4kHz 192kHz) 6. Support Master & Slave Mode 7. Serial P I/F: 4-wire serial 8. 5V operation 9. 3V Power Supply Pin for 3V I/F 10. 44pin LQFP Package 11. Ta: -10 to 70C
MS0118-J-01 -2-
2001/11
ASAHI KASEI
[AK4584]
n u*bN*}
INT0 INT1 RX1 RX2 RX3 RX4
RX1 RX2 OPS1-0 RX3 RX4 TX2E TX2 TX1E TX1
R
TX1 TX2 PDN
AVDD AVSS DVDD DVSS LIN RIN
LIN
IPS1-0
DIR
R_LRCK R_BICK R_DATA R_MCLK
T_LRCK T_BICK T_DATA T_MCLK
DIT
TX3E
TX3
TX3 DZF
A_LRCK
D_LRCK
LOUT
IPGA
RIN
ADC
DATT HPF
A_BICK A_DATA A_MCLK
Audio Interface
D_BICK D_DATA D_MCLK
LOUT ROUT LRCK BICK SDTO SDTI M/S TVDD
DATT SMUTE
DAC
ROUT LRCK BICK SDTO
XTO XTI PVDD PVSS VREF
SDTI
X'tal OSC
MCLK Selector
Divider
MCKI
MCKO1
VCOM MCKO1 MCKO2 DMCK XTALE
Block Diagram
MCKO2
Control Register
CDTO CDTI CCLK CSN
MS0118-J-01 -3-
2001/11
ASAHI KASEI
[AK4584]
n I*[_S"OKCh
AK4584VQ AKD4584 -10 +70C AK4584*]--p{*[h 44pin LQFP (0.8mm pitch)
n s""z'u
TEST1
PVDD
AVDD
PVSS
44 43 42 41 40 39 38 37 36 35 34 TEST2 RX3 NC RX4 PDN INT0 INT1 CDTI CDTO CCLK CSN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 XTALE XTI/MCKI TEST3 DMCK DVDD DVSS TVDD 33 32 31 30 29 28 27 26 25 24 23 ROUT LOUT VCOM DZF M/S LRCK BICK SDTI SDTO MCKO2 MCKO1
AK4584VQ
Top View
MS0118-J-01 -4-
XTO
TX1
TX2
TX3
AVSS
VREF
RX2
RX1
RIN
LIN
R
2001/11
ASAHI KASEI
[AK4584]
s"*^@"\ No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Pin Name TEST2 RX3 NC RX4 PDN INT0 INT1 CDTI CDTO CCLK CSN TEST3 TX1 TX2 XTALE TX3 DVDD DVSS TVDD XTO XTI MCKI DMCK I/O I I I I I O O I O I I I O O I O O I I I Function Test 2 Pin (Internal pull-down pin) Receiver Input 3 with Amp for 0.2Vpp NC Pin (No Internal bonding pin, Fixed to "AVSS") Receiver Input 4 with Amp for 0.2Vpp Power-Down Mode Pin "H": Power up, "L": Power down reset and initialize the control register. Interrupt 0 Pin Interrupt 1 Pin Control Data Input Pin Control Data Output Pin Control Data Clock Pin Chip Select Pin Test 3 Pin (Fixed to AVSS) Transmitter 1 Output Pin Transmitter 2 Output Pin X'tal Osc Enable Pin "H" : Enable, "L" : Disable Transmitter 3 Output Pin Digital Power Supply Pin, 4.75 5.25V Digital Ground Pin Output Buffer Power Supply Pin, 2.7 5.25V X'tal Output Pin X'tal Input Pin External Master Clock Input Pin MCKO1 Disable Pin "H" : MCKO1 "L" output, "L" : MCKO1 output
MS0118-J-01 -5-
2001/11
ASAHI KASEI
[AK4584]
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
MCKO1 MCKO2 SDTO SDTI BICK LRCK M/S DZF VCOM LOUT ROUT AVSS AVDD VREF RIN LIN PVDD R PVSS RX1 TEST1 RX2
O O O I I/O I/O I O O O O I I I I I I
Master Clock Output 1 Pin Master Clock Output 2 Pin Audio Serial Data Output Pin Audio Serial Data Input Pin Audio Serial Data Clock Pin Input / Output Channel Clock Pin Master / Slave Mode Pin "H" : Master Mode, "L" : Slave Mode Zero Input Detect Pin Common Voltage Output Pin, AVDD/2 Bias voltage of ADC inputs and DAC outputs. Lch Analog Output Pin Rch Analog Output Pin Analog Ground Pin Analog Power Supply Pin, 4.75 5.25V Voltage Reference Input Pin, AVDD Used as a voltage reference by ADC & DAC. VREF is connected externally to filtered AVDD. Rch Analog Input Pin Lch Analog Input Pin PLL Power Supply Pin, 4.75 5.25V External Resistor Pin for PLL 13k 1% resistor should be connected to PVSS externally. PLL Ground Pin Receiver Input 1 with Amp for 0.2Vpp Test 1 Pin (Internal pull-down pin) Receiver Input 2 with Amp for 0.2Vpp
Note: All input pins except pull-down pins should not be left floating.
MS0118-J-01 -6-
2001/11
ASAHI KASEI
[AK4584]
*a`I*A`a'eSi (AVSS, DVSS, PVSS=0V; Note 1) Parameter Symbol Power Supplies: Analog AVDD Digital DVDD PLL PVDD Output Buffer TVDD |AVSS - DVSS| (Note 2) GND1 |AVSS - PVSS| (Note 2) GND2 Input Current, Any Pin Except Supplies IIN Analog Input Voltage (VREF, LIN, RIN pins) VINA Digital Input Voltage 1 (Except RX1-4, BICK, LRCK pins) VIND1 Digital Input Voltage 2 (RX1-4 pins) VIND2 Digital Input Voltage 3 (BICK, LRCK pins) VIND3 Ambient Temperature (powered applied) Ta Storage Temperature Tstg Note: 1. "dI`SAO"hs"E`I*e'lA**B Note: 2. AVSSAE DVSS, PVSSIAi*OO"hE*U`A*B
min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -10 -65
max 6.0 6.0 6.0 6.0 0.3 0.3 10 AVDD+0.3 DVDD+0.3 PVDD+0.3 TVDD+0.3 70 150
Units V V V V V V mA V V V V C C
'*O: I'l'|1/2*OE*AZg--p1/2*e**AfoCX"jo*eAE eU**B U1/2*A'E*iI"(R)*iI*U*OeUn*B
**"(R)*i*OE* (AVSS, DVSS, PVSS=0V; Note 1) Parameter Power Supplies Analog (Note 3) Digital PLL Output Buffer Voltage Reference (Note 4) Symbol AVDD DVDD PVDD TVDD VREF min 4.75 4.75 4.75 2.7 3.0 typ 5.0 5.0 5.0 3.0 max 5.25 AVDD AVDD DVDD AVDD Units V V V V V
Note: 1. "dI`SAO"hs"E`I*e'lA**B Note: 3. AVDD, DVDD, PVDD, TVDDI"dOE--*aV*[P"X*l--*e*K--vI eUn*B Note: 4. 'E*iI*AVREF"d AVDDAE"EA*B
'*O: -{f*[^V*[gEL*UeAe*OE*ESOIZg--pESOAI*A"-ZAI*O"C*(c)EU*IA *\*'*O*B
MS0118-J-01 -7-
2001/11
ASAHI KASEI
[AK4584]
Ai*O"A* (Ta=25C; AVDD, DVDD, PVDD, TVDD=5.0V; AVSS=DVSS=PVSS=0V; VREF=AVDD; fs=44.1kHz, 96kHz, 192kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Data; Measurement frequency=10Hz 20kHz at fs=44.1kHz, 10Hz 40kHz at fs=96kHz; 10Hz 80kHz at fs=192kHz; unless otherwise specified) Parameter min typ max Units Input PGA Characteristics: Input Voltage (Note 5) fs=44.1kHz, AIN=0.6 x AVDD 2.8 3.0 3.2 Vpp fs=96kHz, AIN=0.62 x AVDD 2.9 3.1 3.3 Vpp Input Resistance 5 10 15 k Step Size 0.2 0.5 0.8 dB Gain Control Range 0 18 dB ADC Analog Input Characteristics: IPGA=0dB Resolution 24 Bits S/(N+D) (-0.5dBFS) fs=44.1kHz 84 90 dB fs=96kHz 80 88 dB DR (-60dBFS) fs=44.1kHz, A-weighted 94 100 dB fs=96kHz 88 96 dB S/N fs=44.1kHz, A-weighted 94 100 dB fs=96kHz 88 96 dB Interchannel Isolation 90 100 dB Interchannel Gain Mismatch 0.2 0.5 dB Gain Drift 20 ppm/C Power Supply Rejection (Note 6) 50 dB DAC Analog Output Characteristics: Resolution 24 Bits S/(N+D) (0dBFS) fs=44.1kHz 88 94 dB fs=96kHz 86 92 dB fs=192kHz 84 dB DR (-60dBFS) fs=44.1kHz, A-weighted 98 104 dB fs=96kHz 90 98 dB fs=192kHz 85 dB S/N fs=44.1kHz, A-weighted 98 104 dB fs=96kHz 90 98 dB fs=192kHz 85 dB Interchannel Isolation 90 100 dB Interchannel Gain Mismatch 0.2 0.5 dB Gain Drift 20 ppm/C Output Voltage (Note 7) 2.8 3.0 3.2 Vpp Load Resistance 5 k Load Capacitance 25 pF Power Supply Rejection (Note 6) 50 dB Note: 5. IPGA=0dBZI"u--I"dItXP*[ (0dB)*B Note: 6. VREFs"I"de'eEA*A AVDD, DVDD, PVDD, TVDDE1kHz, 50mVppI*OE*"g *d*o1/2*e**B Note: 7. VREF"dE"a--aU**B Vout = 0.6 x VREF*B
MS0118-J-01 -8-
2001/11
ASAHI KASEI
[AK4584]
Parameter Power Supplies Power Supply Current Normal Operation (PDN = "H") AVDD PVDD (fs=44.1kHz) DVDD+TVDD (fs=44.1kHz) (fs=96kHz) Power-down mode (PDN = "L") (Note 8) AVDD PVDD DVDD+TVDD
min
typ
max
Units
23 12 24 36 10 10 10
35 18 36 54 100 100 100
mA mA mA mA A A A
Note: 8. `SAIfBW^"u--Is" DVDDU1/2I DVSSEOEA'e1/2ZI'lA**B
S/PDIF RECEIVER"A*
(Ta=25C; AVDD, DVDD, PVDD=4.75 5.25V; TVDD=2.7 5.25V) Parameter Symbol min Input Resistance Zin Input Voltage VTH 200 Input Hysteresis VHY Input Sample Frequency fs 32 typ 10 50 Max Units k mVpp mV kHz
192
MS0118-J-01 -9-
2001/11
ASAHI KASEI
[AK4584]
tB^"A* (Ta=-10 70C; AVDD, DVDD, PVDD=4.75 5.25V; TVDD=2.7 5.25V; fs=44.1kHz; DEM=OFF) Parameter Symbol min typ max ADC Digital Filter (Decimation LPF): Passband (Note 9) 0.005dB PB 0 19.76 -0.02dB 20.02 -0.06dB 20.20 -6.0dB 22.05 Stopband SB 24.34 Passband Ripple PR 0.005 Stopband Attenuation SA 80 Group Delay (Note 10) GD 31 Group Delay Distortion GD 0 ADC Digital Filter (HPF): Frequency Response (Note 9) -3dB FR 0.9 -0.5dB 2.7 -0.1dB 6.0 DAC Digital Filter: Passband (Note 9) 0.01dB PB 0 20.0 -6.0dB 22.05 Stopband SB 24.1 Passband Ripple PR 0.005 Stopband Attenuation SA 75 Group Delay (Note 10) GD 30 DAC Digital Filter + SCF + SMF: Frequency Response: FR 0 20kHz -0.1 40kHz (Note 11) -0.2 80kHz (Note 12) -1.0
Units kHz kHz kHz kHz kHz dB dB 1/fs s Hz Hz Hz kHz kHz kHz dB dB 1/fs
dB dB dB
Note: 9. Se*U**"A*IZu"g*"I (VXeT"vS"OOE*[g fs )E"a--aU**B --a|I*APB=20.02kHz (@-0.02dB)I 0.454 x fsA**BSe"I kHzSi*EU**B 1 Note: 10. fBW^tB^Eaee'xZZA*A ADC*"IAi*O*M*"u--IeA(c)c--1/4lI 24rbgf*[^ ADC*o--IOEWX^EZbgeeUAIZSOA**B DAC*"I 24rbgf*[^ DAC"u--IOEWX^EZbgeA(c)cAi*O*M**o--IeeUAI ZSOA**B Note: 11. fs=96kHzZ*B Note: 12. fs=192kHzZ*B
MS0118-J-01 - 10 -
2001/11
ASAHI KASEI
[AK4584]
DC"A*
(Ta=-10 70C; AVDD, DVDD, PVDD=4.75 5.25V; TVDD=2.7 5.25V) Parameter Symbol min High-Level Input Voltage (Except XTI pin) VIH 2.2 (XTI pin) VIH 70%DVDD Low-Level Input Voltage (Except XTI pin) VIL (XTI pin) VIL Input Voltage at AC Coupling (XTI pin, Note 13) VAC 40%DVDD High-Level Output Voltage (Except TX1-3, DZF pins : Iout=-400A) VOH TVDD-0.5 (TX1-3 pin : Iout=-400A) VOH DVDD-0.5 (DZF pin : Iout=-400A) VOH AVDD-0.5 Low-Level Output Voltage (Iout=400A) VOL TX Output Voltage Level (Note 14) VOH 0.4 Input Leakage Current Iin Note: 13. XTIs"EJbvS"OR"f"T*U`1/2*e* (Figure 3ZQ*AE )*B Note: 14. Figure 7ZQ*AE*B typ 0.5 Max 0.8 30%DVDD 0.5 0.6 10 Units V V V V Vpp V V V V V A
MS0118-J-01 - 11 -
2001/11
ASAHI KASEI
[AK4584]
XCb"O"A* (Ta=-10 70C; AVDD, DVDD, PVDD=4.75 5.25V, TVDD=2.7 5.25V; CL=20pF) Parameter Symbol min typ Master Clock Timing Crystal Resonator External Clock Frequency Frequency Pulse Width Low Pulse Width High Frequency Duty Cycle (Note 15) Frequency Duty Cycle 11.2896 11.2896 0.4/fCLK 0.4/fCLK 11.2896 40 5.6448 40 32 32 88.2 176.4 45 50 50 50
max 24.576 36.864
Units MHz MHz ns ns MHz % MHz % kHz kHz kHz kHz % %
fCLK tCLKL tCLKH fMCK dMCK fMCK dMCK fPLL fsn fsd fsq
MCKO1 Output MCKO2 Output
24.576 60 18.432 60 192 48 96 192 55
PLL Clock Recover Frequency LRCK Frequency Normal Speed Mode (DFS0="0", DFS1="0") Double Speed Mode (DFS0="1", DFS1="0") Quad Speed Mode (DFS0="0", DFS1="1") Duty Cycle Slave mode Master mode Audio Interface Timing Slave mode BICK Period BICK Pulse Width Low Pulse Width High LRCK Edge to BICK "" (Note 16) BICK "" to LRCK Edge (Note 16) LRCK to SDTO (MSB) (Except I2S mode) BICK "" to SDTO SDTI Hold Time SDTI Setup Time Master mode BICK Frequency BICK Duty BICK "" to LRCK BICK "" to SDTO SDTI Hold Time SDTI Setup Time
tBCK tBCKL tBCKH tLRB tBLR tLRS tBSD tSDH tSDS fBCK dBCK tMBLR tBSD tSDH tSDS
81 33 33 20 20 20 20 20 20 64fs 50 -20 -20 20 20 20 20
ns ns ns ns ns ns ns ns ns Hz % ns ns ns ns
Note: 15. SO*"N*bN"u--II*e**A DutyI*U*OIAUn*B Note: 16. IKSi'lI LRCKIGbWAE BICKI ""*dEcEaeEK'eAU**B
MS0118-J-01 - 12 -
2001/11
ASAHI KASEI
[AK4584]
Parameter Control Interface Timing CCLK Period CCLK Pulse Width Low Pulse Width High CDTI Setup Time CDTI Hold Time CSN "H" Time CSN "" to CCLK "" CCLK "" to CSN "" CDTO Delay CSN "" to CDTO Hi-Z Reset Timing PDN Pulse Width RSTADN "" to SDTO valid (Note 17) (Note 18)
Symbol tCCK tCCKL tCCKH tCDS tCDH tCSW tCSS tCSH tDCD tCCZ tPD tPDV
min 200 80 80 40 40 150 50 50
typ
max
Units ns ns ns ns ns ns ns ns ns ns ns 1/fs
45 70 150 516
Note: 17. AK4584I PDN = "L"ASZbgeU**B Note: 18. RSTADNrbg--*aA(c)cI LRCKN*bNI "In*"A**B "
MS0118-J-01 - 13 -
2001/11
ASAHI KASEI
[AK4584]
n ^C~"O"gOE
1/fCLK VIH MCLK VIL tCLKH 1/fs VIH LRCK VIL tBCK VIH BICK VIL tBCKH fMCK tBCKL tCLKL
MCKO dMCK dMCK
Clock Timing
50%TVDD
MS0118-J-01 - 14 -
2001/11
ASAHI KASEI
[AK4584]
VIH LRCK VIL tBLR tLRB VIH BICK VIL tLRS tBSD
SDTO tSDS tSDH
50%TVDD
VIH SDTI VIL
Audio Interface Timing (Slave mode)
LRCK
50%TVDD
tMBLR
dBCK 50%TVDD
BICK
tBSD
SDTO tSDS tSDH
50%TVDD
VIH SDTI VIL
Audio Interface Timing (Master mode)
MS0118-J-01 - 15 -
2001/11
ASAHI KASEI
[AK4584]
VIH CSN VIL tCSS tCCKL tCCKH VIH CCLK VIL tCDS CDTI C1 C0 tCDH VIH R/W VIL Hi-Z
CDTO
WRITE/READ Command Input Timing
tCSW VIH CSN VIL tCSH VIH CCLK VIL
VIH CDTI D2 D1 D0 VIL Hi-Z
CDTO
WRITE Data Input Timing
MS0118-J-01 - 16 -
2001/11
ASAHI KASEI
[AK4584]
VIH CSN VIL
VIH CCLK VIL
VIH CDTI A1 A0 VIL tDCD CDTO Hi-Z D7 D6 50%TVDD
READ Data Output Timing 1
tCSW VIH CSN VIL tCSH VIH CCLK VIL
VIH CDTI VIL tCCZ Hi-Z
CDTO
D2
D1
D0
50%TVDD
READ Data Output Timing 2
MS0118-J-01 - 17 -
2001/11
ASAHI KASEI
[AK4584]
VIH CSN VIL tPDV
SDTO
50%TVDD
tPD PDN VIL
Power Down & Reset Timing
MS0118-J-01 - 18 -
2001/11
ASAHI KASEI
[AK4584]
"(R)*i*a-3/4
n foCX"a*"I*M*pX
DAC, SDTOI ADC, SDTI, DIR*o--I(c)c*A DITI ADC, SDTI*o--I(c)cXCbEaee AI"u--I`I`U**B 1 U1/2*A IR, DITX*[*epXa`I`AU**B*}'IXCbI-1/4`O (DAC1-0 etc)IOEWX^IrbgE D `IU**B*U*xIOEWX^}bvI *u*U*x*a-3/4*vI* (AhOEX 08H)ZQ*AEA*B
HPF IPGA ADC DATT
DAC1-0
DEM
DATT DAC SMUTE
SDTI
PCM1-0
SDTO DIR
DIT1-0
DIT
DIT1-0
Figure 1. Connection Input Source & Output Source
n }X^N*bN"(R)*i*[h
AK4584IN*bN\*[XAEA*A PLLZg--p*e(c)X'tal(SO*"N*bN\*[XaSUYU* )Zg--p*e(c)I CM1-0rbgA*Y'eeU* (Table 1)*B Mode 2AI PLL UnlockEEeAEN*bN\*[XZ(c)"(R)"IE X'talE*O e`OieU**B Mode 3AIN*bN\*[XI X'talEOEA'eA**AlXe*[^X"TMIRXf*[^Ij^ AU**BMode 2, 3AI PLLAE X'talIZu"g*"*dEcEaeE*Y'e*eAE**U**B XTALE="L"(c) AXTL1-0rbg ="11"IZ*A ode 0AX'tal"-*UI'aZ~U**BCM1-0rbgI*Su'lI "01"A**B M CM1-0rbg*Oe`O|1/2*e**A*M*pXIZ(c)"(R)"IE*Oe`OieUnIA*AAhOEX 08HA*o--I\*[X"K X*A`I`A*B Mode 0 1 2 3 UNLOCK PLL X'tal Clock Source ON PLL OFF ON X'tal 0 ON ON PLL 1 0 1 ON ON X'tal 1 1 ON ON X'tal ON : "-*U(Power-up), OFF : 'aZ~ (Power-down) : XTALE="L"(c)AXTL1-0rbg ="11"IZ OFF*AeESOION Table 1. Clock Operation Mode Select CM1 0 0 CM0 0 1
Default
MS0118-J-01 - 19 -
2001/11
ASAHI KASEI
[AK4584]
n }X^N*bN*o--I
AK4584I}X^N*bN*o--Is" 2s"Z*U**}X^N*bN\*[XAEA B PLLASJoS1/2N*b N*AU1/2ISO*tI X'talA"-*U1/2N*bNICc(c)`I`AU**B PLL*[hZ*A}X^N*bN*o--I (MCKO1 or MCKO2)I fsE`I*e"aI OCKS1-0rbgA*Y'eU* (Table 2)*B X'tal*[hyNSO*"N*bN *[hZ* A }X^N*bN*o--I (MCKO1 or MCKO2)I 1"{AE1/2"{*o--IeU* (Table 3)* B U1/2*A MCKO1I DMCK s"AfBZ*[uAU**BDMCK="H"A"L"*o--I (fBZ*[u)*A DMCK="L"A'E*i*o--IA**BLL*[ P hZ*ASe*Y'e*[h-E`IA"\E Table 2IaeE*OEA eU**B Mode 0AI 96kHzT"vS"OI fsEI T|*[gUn*B OCKS1-0rbgI*Su'lI "01"A**B Mode 0 1 2 3 OCKS1 0 0 1 1 OCKS0 0 1 0 1 MCKO1 512fs 256fs 128fs 64fs MCKO2 256fs 128fs 64fs 32fs fs 48kHz 96kHz 192kHz 192kHz
Default
Table 2. Master Clock Output Frequency Select (PLL Mode) X'tal MCKO1 MCKO2 11.2896MHz 11.2896MHz 5.6448MHz 12.288MHz 12.288MHz 6.144MHz 24.576MHZ 24.576MHz 12.288MHz Table 3. Master Clock Output Frequency Select (X'tal Mode) *EnCG"h ADC(AK5394) DAC(AK4394) AK4584 AE ISO*"E*U`*e*UIN*bNI`I`*u-@ AK4584}X^*[*[hAZg--p*A AK5394, AK4394XOE*[u*[hAZg--p*e*e*I*U`--aA**B AK5394 AK4394 MCKO2 MCKO1 N*bN*o--I 256fs 512fs 'E*i` 128fs 256fs 2"{` 64fs 128fs 4"{` Table 4. Clock Select for AK5394 & AK4394
MS0118-J-01 - 20 -
2001/11
ASAHI KASEI
[AK4584]
n VXeN*bN }X^N*bN (MCLK)I XTIs"AEXTOs"ISOE X'tal"-*UZq*U`*e(c)*AU1/2I XTOs"I*[v"E AXTIs"ESO*"(c)c CMOSOExN*bN"u--I*e*A ACJbvA 40%DVDDE*aIOExIN*b N"u--I*e*Aa-I"a` I PLLASJoS1/2N*bN(c)c"3/4ceU**B}X^N*bNZu"g*"I*A X'tal *[hyNSO*"N*bN*[hI*e**A ICKS1-0rbgA*Y'e(Table 5)e*ADFS1-0rbgA'E*i`*[h*A 2"{`*[h*A 4"{`*[h`I`U* (Table 6)*B 4"{`*[hAI*AADCIp**[_E"eU**B
X'tal"-*UZqZg--p*e*e*I*ASO*"E*x--e--E (XTI/XTOAE DVSSSO )*K--vA**B SO*"N*bN"u--I*e*e*I*A DVDDI CMOSOEx*M*'1/4*U"u--I*e*e*AE*A 40%DVDDE*aI"dI *M* ACJbvA"u--I*e*e* eU**B XOE*[u*[hAI}X^N*bNAE LRCKI"Su*e*K--vI eU**AE`S*ie*K--vI eU n*BU1/2*A"(R)*i' (PDN="H"(c)AR"g**[OEWX^EaeAA PWVRNrbg "H"IZ )ESO*"N*bN (MCLK, BICK, LRCK)Z~AIUn*BecIN*bNYeE*e**A"a*"E_Ci~bNE *WbNZg--pAe1/2*A"d----e"(R)*iU*iEEeA"\* eU**BN*bNZ~e*e*E Ip**[_E"*o`O (PDN = "L"U1/2IR"g**[OEWX^EaeAA PWVRNrbg "L"E*Y'e )A *B"--lE*A}X^*[*[hAIp**[_E"ZESOI*A X'tal"-*UZqAA"-*UA-(c)*ASO*"N* bN (MCLK)Y*e(c)*A PLL"(R)*iAA*B MCLK Normal Double Quad ICKS1 ICKS0 (DFS1-0 = "00") (DFS1-0 = "01") (DFS1-0 = "10") 0 0 256fs N/A N/A 0 1 384s N/A N/A 1 0 512fs 256fs 128fs 1 1 768fs 384fs 192fs Table 5. Master Clock Input Frequency Select (X'tal Mode) DFS1 0 0 1 1 DFS0 0 1 0 1 Sampling Rate Default
Mode 0 1 2 3
Default
'E*i` 2"{` 4"{` N/A Table 6. Sampling Speed MCLK Double 128fs 192fs 256fs 384fs
MCLK Normal 256fs 384fs 512fs 768fs MCLK Normal 256fs 384fs 512fs 768fs
fs=44.1kHz 11.2896MHz 16.9344MHz 22.5792MHz 33.8688MHz
fs=88.2kHz N/A N/A 22.5792MHz 33.8688MHz
MCLK Quad 64fs 96fs 128fs 192fs
fs=176.4kHz N/A N/A 22.5792MHz 33.8688MHz
MCLK MCLK Double Quad fs=48kHz fs=96kHz 12.288MHz 128fs N/A 64fs 18.432MHz 192fs N/A 96fs 24.576MHz 256fs 24.576MHz 128fs 36.864MHz 384fs 36.864MHz 192fs Table 7. Master Clock Frequencies example
fs=192kHz N/A N/A 24.576MHz 36.864MHz
**...*"-*U*[hI 11.2896MHz(c)c 24.576MHzE`IU**B *24.576MHzz|eZu"g*"ISO*"N*bN"u--IIY`IU**B
MS0118-J-01 - 21 -
2001/11
ASAHI KASEI
[AK4584]
n N*bN\*[X
(1) X'talZg--p*e*e*
XTI
XTO
AK4584
Figure 2. X'tal mode - Note: R"f"TI'lI*...**U"(R)ZqEE`U**B 10 40pF) (typ. (2) SO*"N*bNZg--p*e*e*
XTI External Clock XTO AK4584
External Clock
C
XTI
XTO
AK4584
Figure 3. (a) External Clock mode Figure 3. (b) External Clock Mode (Input : CMOS Level) (Input : 40%DVDD) - Note: DVDDE*aIN*bNI"u--IEA*B (3) XTI/XTOZg--pE*e*
XTI
XTO
AK4584
Figure 4. Off mode
n 192kHz`IN*bNSJoSnH "a` *e'aWb^PLLI 32kHz(c)c 192kHzI*bNOE"WZ**A*bNZSOI 20msEA**BU1/2*Al Xe*[^XIT"vS"OZu"g*"*i*n*AU1/2I*A X'talIZu"g*"AEI"aSrEaee*AT"vS"OOE*[g (32k, 44.1k, 48k, 88.2k, 96k, 176.4k, 192k)OEY*oU**B*SOSuAvSA"uZo*MEAE"SuSOeN eU**B
MS0118-J-01 - 22 -
2001/11
ASAHI KASEI
[AK4584]
n oCtF*[Y"u--I
AK4584I 4"u--I RX1-4)E`IU**BSe"u--II*s*1/2*t*[hE`I1/2A"v"a` eAe*A 200mVpp ( I*M*aZo*MA"\A**B IPS1 0 0 1 1 IPS0 Input Data 0 RX1 1 RX2 0 RX3 1 RX4 Table 8. Recovery Data Select
Default
n oCtF*[Y*o--I
TX1-2s"(c)cI RX(c)cZo*M1/2f*[^IX*[*o--I*A TX3s"(c)cI SDTI(c)cIf*[^yNAi*O"u --IA/D*IS*1/2f*[^ IEC60958tH*[}bgE*IS*1/2f*[^yN RX(c)cZo*M1/2f*[^Ie(c) *o--IAU**B TX1-2s"OI*o--II`I`I OPS1-0rbgA*s*A TX3s"OI*o--II`I`I TX1-3*o--II X1E, TX2E, TX3EISerbgA*o--IZ~eAEAU**B T DIT1-0rbgA*sU**B
CrbgI*A*I 5byteOEWX^AR"g**[AU**BR"V...*[}*[h (CT0rbg ="0")I*e**A bit20-23(Audio Channel)OI'1/4*U*`*YI*sAA**B TCHrbg "1"IZIXeOEI*o--IE`I*A Sub frame 1I "1000"(*l )*A frame 2I "0100"(El)Z(c)"(R)"IE*Y'eeU**B TCHrbg "0"I Sub ZI "0000"(Zw'eE)EEeU**B U1/2*A rbgI UDITrbgEaee 2'EeI'(c)c`I`AU**B UDITrbg "0"A"0"OEA'e*A U UDITrbg "1"ASJoS1/2UrbgIUU DIT(c)c*o--IU**BI*[hI PLL*bNZIY`IU**B PLLA"*bNZ*A UrbgI "0"*o--IU**B OPS1 0 0 1 1 OPS0 Output Data 0 RX1 1 RX2 0 RX3 1 RX4 Table 9. Output Data Select for TX1/2
Default
DIT1 0 0 1 1
DIT0 Input Source 0 ADC 1 SDTI 0 DIR 1 N/A Table 10. Output Data Select for TX3
Default
Note: A"*bN*oeOEaI V-bitf*[^--n ZuSuI"jSuA*B 1 **iEf*[^"]`--AAEA"\* eU**B
MS0118-J-01 - 23 -
2001/11
ASAHI KASEI
[AK4584]
n oCtF*[Y*M*"u*o--InH
0.1uF 75 Coax 75 RX
AK4584
Figure 5. Consumer Input Circuit (Coaxial Input) Note 1 : Coaxial"u--IAI*A--x*U*e RX"u--Ip^*["(c)cJbvS"O*emCYOEx50mVz |e*e** A OEe"(R)*i*eA"\* eU** B JbvS"OEaeE*[*V*[hA*B Note 2 : "ZRlN^IO"hyN*I'[*aeIO"hI PC{*[h*aA AK4584I PVSSAE'aC"s*[ _"XA*U`A*B Optical Receiver Optical Fiber O/E
470 RX
AK4584
Figure 6. Consumer Input Circuit (Optical Input) Coaxial"u--II*e**A RXIZo*MOExI"n*iE*IA* **"I RX"u--ISOAN*Xg*[NNEae A E"z*uISOEV*[hp^*[""ueeECA'*OA*B AK4584I TX*o--Iobt@"a` *ASO*"'i*RAE`gY*iA0.5V+/-20%-`U**BFigure 7AI T1I 1:1 Ig"XA**B 330 TX 100 DVSS T1 Figure 7. TX External Resistor Network 75 cable
MS0118-J-01 - 24 -
2001/11
ASAHI KASEI
[AK4584]
n T"vS"OZu"g*"OEY*oAEvSG"t@VXOEY*o T"vS"OZu"g*"OEY*o*u-@AEA 2Zi--I*u-@A"\A**B XTL1-0rbgEaee*A X'talIZu"g*"AEI"aSrA
Zu"g*"OEY*oA*AR"g**[OEWX^I FS3-0rbgE*o--IU**B"aSr*e X'talIZu"g*"IOEWX^E aee`I`AU**B XTALE="L"(c)AXTL1-0rbg ="11"I*e*EI*A*...*"-*UnHI'aZ~*AlXe *[^XIT"vS"OZu"g*"*i*nG"R*[hAR"g**[OEWX^I FS3-0rbgE*o--IU**B FS30rbgI*Su'lI "0000"A**B XTL1 0 0 1 1 XTL0 X'tal Frequency 0 11.2896MHz Default 1 12.288MHz 0 24.576MHz 1 lXe*[^XZg--p Table 11. Reference X'tal Frequency
XTL1-0rbg ="11"ESO Register Output fs FS3 0 0 0 0 1 1 1 1 FS2 0 0 0 0 0 0 1 1 FS1 0 0 1 1 0 1 0 1 FS0 0 1 0 1 0 0 0 0 44.1kHz Reserved 48kHz 32kHz 88.2kHz 96kHz 176.4kHz 192kHz 3% 3% 3% 3% 3% 3% 3% Table 12. fs Information Clock comparison
XTL1-0rbg ="11" Consumer Mode Pro Mode (Note 1) Byte3 Byte0 Byte4 Bit3,2,1,0 Bit7,6 Bit6,5,4,3 0000 01 0000 0001 (others) 0000 0010 10 0000 0011 11 0000 (1000) 00 1010 (1010) 00 0010 (1100) 00 1011 (1110) 00 0011
Note 1. When consumer mode, Byte3 Bit3-0 are copied to FS3-0. U1/2*AvSG"t@VX*i*nG"R*[hA*AR"g**[OEWX^I PEMrbgE*o--IU**Bec I*i*nI*ASZbgZ (CS12rbg ="0"IZ )*Al1I*i*nG"R*[hU**AR"g**[OEWX ^I CS12rbg "1"E*eAEAl 2E*Oe`O|eAEaA"\A**B PEM bit Byte0 Bit3,4,5 0 OFF 0X100 1 ON 0X100 Table 13. PEM in Consumer Mode Pre-emphasis Byte0 Bit2,3,4 OFF 100 ON 100 Table 14. PEM in Pro Mode Pre-emphasis
PEM bit 0 1
MS0118-J-01 - 25 -
2001/11
ASAHI KASEI
[AK4584]
n G*["-*ZI*--*
INT1-0s" "H"EEe--voEIEI 8A eU**B (1) UNOCK: PLLA"*bN*o`OEEeAE "H"EEeU**B *vSA"uZo*MAE* A a-IISOSu*-E*e*EA"*bNAEEe U**B (2) PAR: pSeBG*[ (oCtF*[YG*[SU ) SeTutOE*[-E*X*Ve*AAhOEX 0EH"CY*AESZbgeU**B Non-Linear PCMrbgXgS*[OEY*o*B
(3) AUTO:
(4) DTSCD: DTS-CDrbgXgS*[OEY*o*B (5) AUDION:Non-AudioOEY*o*B (6) PEM: (7) V: (8) FS: vSG"t@VXOEY*o*B oSfBeBOEY*o*B FSOEY*o*B FS3-0rbg*I*eAE*A 1TutOE*[ISO*A "H"EEeU**B FS3-0rbgI"a--eI C-bit*aI fs-bitU1/2I X'talEaeeZu"g*"OEY*oOEE 12ZQ*AE 1u (Table )A*A *bN-E`OnIf*[^AE"aSreU**BAhOEX 0EH"CY*AESZbgeU**B
*aL(1)(c)c (8)I--voI ORSe INTs"E*o--IeU**B'A*ASe--voIe1/4eI}XNrbgA}XNA *AI--voI INTs"EI"1/2feUn ('A*A 0EHIOEWX^EI"1/2feU* )*B INT0*o--II`SAI--v o**i"(R)*iE*oeA1/2OEa*A 1024/fs(EFH1-0rbgA*I*XA )SOI"H"I*o`O*UZ*U**BU1/2*A PARrbg AE FSrbgIe"x "1"EEeAEI'l*UZ*e*AAhOEX0EH"CY*AESZbgeU**B A"*bNZIlXe*[^XrbgESO*eOEWX^I*X*Ve*A`OI'l*UZ*U**B*Su*o`O AI*A INT0s"I UNLOCK, PARrbg--LOEoE*AU1/2 INT1s"I AUTO, DTSCD, AUDION, VDIRrbg --LOEoEEAAU**B PLL OFFI*e**A INT1-0s"I "L"EEeU**B Register DTSCD AUDION PEM VDIR FS x x x x x x x x x x x x x x x 1 x x x x x 1 x x x x x 1 x x x x x 1 x x x x x 1 Table 15. Error Handling (x : Don't Care) Pin SDTO "L" Previous Data Output Output Output Output Output Output
UNLOCK 1 0 0 0 0 0 0 0
PAR x 1 0 0 0 0 0 0
AUTO x x 1 x x x x x
TX Output Output Output Output Output Output Output Output
Note : Table 15I SDTOI"u--I\*[XAEA*AIR`I`1/2*e*I*\A**B D
MS0118-J-01 - 26 -
2001/11
ASAHI KASEI
[AK4584]
Error (UNLOCK, PAR,..) INT0 pin
(Error)
Hold Time (max: 4096/fs)
INT1 pin Register (PAR, FS) Register (others) Command MCKO,BICK,LRCK (UNLOCK) MCKO,BICK,LRCK (except UNLOCK) SDTO (UNLOCK) SDTO (PAR error) SDTO (others) Previous Data
Hold Time = 0
Hold "1"
Reset
READ 0EH
Free Run (fs: around 20kHz)
Normal Operation Figure 8. INT0/1 pin Timing
MS0118-J-01 - 27 -
2001/11
ASAHI KASEI
[AK4584]
PDN pin = "L" to "H" Initialize Read 0EH
INT0/1 pin = "H"
Yes
No
Release Muting
Mute DAC Output
Read 0EH Each Error Handling
No
INT0/1 pin = "H"
Yes
Figure 9. Error Handling Sequence Example
n Non-PCM/DTS-CDf*[^XgS*[OEY*o@"\
AK4584I Non-PCMf*[^XgS*[IOEY*o@"\Z*U**B Dolby "AC-3 Data Stream in IEC60958 Interface" E*'1/2 32bit ModeI Non-PCMf*[^vSA"uOEY*oeeZ*AUTOrbg "1"EEeU**BvS A A"uI 96bit sync codeI 0x0000, 0x0000, 0x0000, 0x0000, 0xF872 and 0x4E1FA*\*eU**BZYI4096tOE *[Async codeOEY*oeE*e**A*XE codeOEY*oeeUA AUTOrbgI "0"A**BU1/2*AIv sync SA"uOEY*oe1/2*e**A codeE`A 2oCg(Pc, Pd)OEWX^ESi"[U**B"--lE TS-CDI sync D f*[^vSA"uOEY*oeeAE DTS-CDrbg "1"EEeU**BZYI4096tOE*[A sync codeOEY*o eE*e**A*XE codeOEY*oeeUA DTS-CDrbgI "0"A**B sync
MS0118-J-01 - 28 -
2001/11
ASAHI KASEI
[AK4584]
n I*[fBIC"^tF*[XtH*[}bg
5Zi--If*[^tH*[}bg (Table 16) DIF2-0rbgA`I`AU**B`S*[hAEa MSBt@*[Xg*A 2'sR "vS*"gIf*[^tH*[}bgASDTOI BICKI--eA*o--Ie*A SDTII BICKI--*aeA beU**BI*[fBIC"^tF*[XI}X^*[hAEXOE*[u*[hE`IU**B}X^*[hA I LRCKAE BICKI*o--IEEe*AXOE*[u*[hAI"u--IEEeU**B}X^*[hZI LRCKZu"g*"AE BICK Zu"g*"Ie1/4e fsAE 64fsA**B 20rbgEItH*[}bg (Mode0-1)AI*ATutOE*[I SB`*OeZIAceU**B Mode2-4AIE4 L rbgI Auxf*[^A**BFigure 10Erbg*\*Z|U**B SDTI"u--ItH*[}bgI*AMode2, 3, 4 16 20rbgAZg--p*e*e*EI*Af*[^IELSBEI "0" "u--IA*B
sub-frame of IEC60958
0 34
Aux.
78
11 12
27 28 29 30 31
V U C P
preamble
LSB
MSB
MSB 23
LSB 0
AK4584 Audio Data (SDTO, MSB First)
Figure 10. Bit Structure Mode 0 1 2 3 4 DIF2 0 0 0 0 1 DIF1 0 0 1 1 0 DIF0 0 1 0 1 0 SDTO SDTI 24bit, MSB justified 16bit, LSB justified 24bit, MSB justified 20bit, LSB justified 24bit, MSB justified 24bit, MSB justified 24bit, I2S Compatible 24bit, I2S Compatible 24bit, MSB justified 24bit, LSB justified Table 16. Audio Data Format LRCK H/L H/L H/L L/H H/L BICK 32fs 40fs 48fs 48fs 48fs
Default
MS0118-J-01 - 29 -
2001/11
ASAHI KASEI
[AK4584]
LRCK
0123 9 10 11 12 13 14 15 0 1 2 3 9 10 11 12 13 14 15 0 1
BICK(32fs) SDTO(o) SDTI(i) BICK(64fs) SDTO(o) SDTI(i)
23 22 21 Don't Care 76543 15 14 13 12 10 23 22 21 Don't Care 76543 15 14 13 12 210 23 23 22 21 15 14 13 0123 15 14 13 12 11 10 9 8 23 22 21 7 6 5 4 3 2 1 0 15 14 13 17 18 19 20 31 0 1 2 3 15 14 13 12 11 10 9 8 23 7 6 5 4 3 2 1 0 15 17 18 19 20 31 0 1
SDTO-23:MSB, 0:LSB SDTI-15:MSB, 0:LSB Lch Data Rch Data
Figure 11. Mode 0 Timing
LRCK
012 12 13 24 31 0 1 2 12 13 24 31 0 1
BICK(64fs) SDTO(o) SDTI(i)
23 22 12 11 19 0 8 10 23 22 12 11 19 0 8 10 23
Don't Care
Don't Care
SDTO-23:MSB, 0:LSB SDTI-19:MSB, 0:LSB Lch Data Rch Data
Figure 12. Mode 1 Timing
LRCK
012 20 21 22 23 24 31 0 1 2 20 21 22 23 24 31 0 1
BICK(64fs) SDTO(o) SDTI(i)
23 22 23 22 43210 23 22 43210 43210 23 Don't Care 23
4 3 2 1 0 Don't Care 23 22
23:MSB, 0:LSB Lch Data Rch Data
Figure 13. Mode 2 Timing
MS0118-J-01 - 30 -
2001/11
ASAHI KASEI
[AK4584]
LRCK
0123 21 22 23 24 25 012 21 22 23 24 25 01
BICK(64fs) SDTO(o) SDTI(i)
23 22 23 22 43210 43210 23 22 Don't Care 23 22 43210 43210 Don't Care
23:MSB, 0:LSB Lch Data Rch Data
Figure 14. Mode 3 Timing
LRCK
012 89 24 31 0 1 2 89 24 31 0 1
BICK(64fs) SDTO(o) SDTI(i)
23 22 16 15 23 0 8 10 23 22 16 15 23 0 8 10 23
Don't Care 23:MSB, 0:LSB
Don't Care
Lch Data
Rch Data
Figure 15. Mode 4 Timing
MS0118-J-01 - 31 -
2001/11
ASAHI KASEI
[AK4584]
n }X^*[*[hAEXOE*[u*[hI*Oe`O| }X^*[*[hAEXOE*[u*[hI*Oe`O|I M/Ss"A*sU**B"H"A}X^*[*[h*A "L"AXOE*[u
*[hA**BAK4584}X^*[*[hIZEI*AAK4584(c)c MCKO, BICK, LRCK*o--IeU**B AK4584 XOE*[u*[hIZEI*A AK4584(c)cI MCKOIY*o--Ie*ABICK, LRCKISO*" DSP(c)cY*e*K--v eU*IA*ASO*" DSP(c)c MCKO*Zu1/2 BICK, LRCKYA*B MCKO1/2 BICK, LRCK MCKO1 = Output BICK = Input Slave Mode MCKO2 = Output LRCK = Input MCKO1 = Output BICK = Output Master Mode MCKO2 = Output LRCK = Output Table 17. Master mode/Slave mode
n N*bN"(R)*iAEp**[_E"ISOOEW
AK4584p**[_E"Z*AXOE*[u*[h /}X^*[*[hESOOEWE-*A XTALEs"AN*bN*o--IR" g**[AU**BMCKO1I DMCKs"A*o--IfBZ*[uAU**B PDN pin M/S pin L H L L H H L H H Don't Care default'l "01"OEA'e XTALE pin L CM1-0 bit MCKO1/2 MCKO1 = L MCKO2 = L MCKO1 = Output1) MCKO2 = Output1) MCKO1 = L MCKO2 = L MCKO1 = Output1) MCKO2 = Output1) BICK, LRCK BICK = Input LRCK = Input DIR, CODEC Power Down
BICK = L LRCK = L BICK = Input LRCK = Input BICK = Output LRCK = Output
Power Down
MCKO1 = Output2) Zg--pA MCKO2 = Output2) Table 18. Clock Operation
Normal Operation
Note 1) : DIRp**[_E"*e1/2*AN*bN\*[XI 'tal"-*UZqa-ISO*"N*bNEEeU**B X Note 2) : N*bN\*[XI CM1-0rbgAOE'eeU**B'A*A*[h*O`OZE MCKO*o--I*uSO"IE 'aZ~*eAE eU**B Note: XTALE="L"ASO*"N*bN ACJbvEAZg--p*e*e**A PDNs" "L"E*eZEI*A XTIs" "L"EOEA'eA*B
n fBW^ HPF
ADCI DCItZbgL"ZI1/2EfBW^ HPF"a` U**B HPFI fcI*Afs=44.1kHzZ*A 0.9HzE EAAe*AZu"g*""I fsE"a--aU**B
MS0118-J-01 - 32 -
2001/11
ASAHI KASEI
[AK4584]
n "u--I{S...*[
ADCI`O'iE 37OEx*A 0.5dBXebvI 2ch"AE--IAi*O{S...*[ (IPGA)"a` *AOEa'iE 128Xebv (~...*[gSU )IfBW^{S...*[ ("u--I TT: IATT)"a` U**B--1/4{S...*[IR"g**[I" A AhOEXIOEWX^EATC"e*A MSB "1"I*e*I IPGA*I*A "0"I*e*I IATT*IU**B IPGAIAi*O{S...*[I1/2*AfBW^*uZ(R)E"axA S/Nu`PEOEoE eU*(Table 19)*BcE[ *N*XOEY*o@"\Eaee*Oe`O|mCY'aOEU**B[*N*XOEY*oISe ch"AE--E*sieU**B[*N* XE*e*I^CAEgA-*"IE*Oe`OieU**BI*U^CAEgZSO fsE"a--a*A'E*i` (To)I *[hAI To=256/fs(c)c2048/fs`I`AU**B[*N*XU1/2I^CAEgA IPGA*Oe`Oie`OE IPGAOEWX^E*V'l*`*AE*A`OnI IPGA'lI-OEoEEeU**BU1/2*A^CAEgI1/2I^C }(L/R"AE-- )SZbge*A*`*n3/4*V IPGA'lOI*I*X"(R)*iZnUeU**B[*N*XOEY*o@"\I[ *N*XCl*[urbg (ZCEI)AON/OFFA"\A**B IATTI"a*"SjA*aSOe1/2^Z--*O{S...*[AOEx*Oe`O|1/2*e**AOExSOI*A`a 8031Xebv A\tg`JUU**BI1/2*Oe`O|mCYI`S-*oUn*B Input Gain Setting 0dB +6dB fs=44.1kHz, A-weight 100dB 98dB Table 19. PGA+ADC S/N ZTM1 0 0 1 1 ZTM0 'E*i` 2"{` 0 256/fs 512/fs 1 512/fs 1024/fs 0 1024/fs 2048/fs 1 2048/fs 4096/fs Table 20. Zero Crossing Timeout
+18dB 90dB
Default
n fBG"t@VXtB^R"g**[
IIRtB^Eaee 3Zu"g*"32kHz, 44.1kHz, 48kHz)`IIfBG"t@VXtB^ ( (50/15s"A*"a` A ) U**BDEM1-0rbgAfBG"t@VXtB^R"g**[AU*(Table 21)*B 2"{`*A 4"{`ZEI `IUn*B DEM1 0 0 1 1 DEM0 Mode
0 44.1kHz 1 OFF Default 0 48kHz 1 32kHz Table 21. De-emphasis Control
n *o--I{S...*[
AK4584I MUTESU0.5dBXebv*A 256OExIl"AE--fBW^*o--I{S...*[ (ATT)"a` U**BI{S...*[IDACI`O'iE e"u--If*[^ 0dB(c)c -127dBUAOE*S*AU1/2I~...*[gU**B *Y'e'lSOI`JUI\tg`JUA**B*]AA*A`JU'EXCb"OmCYI"-*Un*B
MS0118-J-01 - 33 -
2001/11
ASAHI KASEI
[AK4584]
n \tg~...*[g@"\
DAC"u--IIfBW^*"E\tg~...*[g@"\"a` U**B\tg~...*[gI SMUTErbgAR"g**[ AU**B SMUTErbg "H"E*eAE 1024LRCKTCNA DACIf*[^ - ("0")UAAel*[V" eU**BSMUTErbg "L"E*eAE - TM - 024LRCKTCNA 1 0dBUA*oeAU**B \tg~...*[gSJZnOEa*A 1024LRCKTCNE"aE*oeeeAEAel*[V"''fe*A"TCNA 0dBUA*oeAU**B \tg~...*[g@"\I*o--I{S...*[AEI"AE--Ae*A*c`*U`e1/2SOOEWA**B
SMUTE 1024/fs 0dB Attenuation (1) (3) 1024/fs
-
GD (2) LOUT / ROUT GD
D Z F p in
(4) 8192/fs
Figure 16. \tg~...*[g@"\AE[*OEY*o@"\ (1) 1024LRCKTCN1024/fs)A"u--If*[^ - ("0")UAAel*[V"eU**B ( (2) fBW^"u--IE`I*eAi*O*o--IIOEQ'x (GD)aU**B (3) 1024LRCKTCNE"aE\tg~...*[g*oeeeAEAel*[V"''fe*A"TCNA 0dBUA*oeAU**B (4) "u--If*[^--1/4lE8192nA`A "0"I*e**AZFs" "H"EEeU**BIOEa*A"u--If*[^ D "0"AE-EeAE*ADZFs"I "L"EEeU**B
MS0118-J-01 - 34 -
2001/11
ASAHI KASEI
[AK4584]
n [*OEY*o@"\
AK4584I DACI L/Rl'EI[*OEY*o@"\Z*U**B L/R--1/4lI"u--If*[^ 8192nA`A "0"I*e**AZFs" "H"EEeU**BIOEa*A"u--If*[^ "0"AE-EeAE DZFs" "L"EEeU**B[ D *OEY*o@"\I DZFErbgA-OEoEAU**BIZ*A--1/4lI DZFs"I*iE "L"A**B PDNs" "L"IZI--1/4lI DZFs"I "L"A**BPDNs"Eaeep**[_E"*oe (PDNs" ="L" "H")Z*A DZFs"I "L" "H"E*IU**BPWVRNrbg "0"IZI*A--1/4lI ZFs"I "L"A**B D RSTDANrbgE "0"*`*AE'1/4E DZFs"I "H"EEe*AIOEa*A 5/fsOEaE 4/fs LSI"a*"SZbg eU**B RSTDANrbgE "1"*`*nA(c)c6/fs 7/fsISO*A DZFs"I "H"*o--I`*AIOEa L"EE " eU**B*aLI RSTDANrbgE "0"*`*nA(c)c5/fsE"aE RSTDANrbgE "1"*`*UeeAE*ASI L "a*"I**iESZbgeE*e* eU**B PWDANrbgE "0"*`*AE'1/4E DZFs"I "H"EEe*AIOEa*A 5/fsOEaE 4/fs LSI"a*"SZbg eU**B PWDANrbgE "1"*`*nA(c)c6/fs 7/fsISO*A DZFs"I "H"*o--I`*AIOEa L"EE " eU**B*aLI PWDANrbgE "0"*`*nA(c)c5/fsE"aE PWDANrbgE "1"*`*UeeAE*A LSI "a*"I**iESZbgeE*e* eU**B PDNs" ="H"(c)APWDANrbg ="1"(c)ARSTDANrbg ="1"AEEA1/2*o`O(c)c/fsOEaE'E*iI[*OEY*o@"\ 1 I1/2I 8192JE"gSJZneU**B
n SZbgAEp**[_E"
AK4584I*APDNs"EaeenH`S`IIp**[_E"AEOEWX^Eaeee*"p**[_E"A"\A* (Table 22)*B"dOE--*aZEI*K PDNs"Ee"x "L""u--IASZbgA*B PDN L PWDITN x 0 x x x x x PWVRN x x 0 x x x x PWADN PWDAN CM1-0 Function x x x All Power-down x x x DIT Power-down x x x VREF Power-down 0 x x ADC Power-down x 0 x DAC Power-down x x 00 X'tal Power-down x x 01 PLL Power-down Table 22. Reset & Power Down Register Initialization Yes No No No No No No
MS0118-J-01 - 35 -
2001/11
ASAHI KASEI
[AK4584]
n VSAR"g**[C"^tF*[X
4*uZ(R)VSA I/Fs" : CSN, CCLK, CDTI, CDTOA*`*YyN"CY*o*sU**B I/F*aIf*[^I Chip address(2bits, C1/0, "00"OEA'e*A ) Read/Write(1bit)*A Register address(MSB first, 5bits)AE Control data(MSB first, 8bits) A*\*eU**Bf*[^`--*M`I CLKI ""ASerbg*o--I*AZo*M`I C ""AZaee*YU**Bf*[^I*` *YICSNI ""A--LOEoEEeU**B CCLKIN*bNXs*[hI MHz(max)A** ANZXEZI 5 B CSN "H"U1/2I "L"EOEA'eA*BbvAhOEXI "00"EOEA'eA**BbvAhOEX "00"ESOI"u--IE`I AI*`*Y-OEoEEeU**B PDNs" ="L"A"a*"OEWX^'lI*SueU**B
CSN 0 CCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CDTI Write CDTO
C1
C0
R/W
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Hi-Z
CDTI Read CDTO
C1
C0
R/W
A4
A3
A2
A1
A0
Hi-Z C1 - C0 : Chip Address (Fixed to "00") R/W : READ / WRITE ("1" : WRITE, "0" : READ) A4 - A0 : Register Address D7 - D0 : Control Data
D7
D6
D5
D4
D3
D2
D1
D0
Hi-Z
Figure 17. Control I/F Timing
MS0118-J-01 - 36 -
2001/11
ASAHI KASEI
[AK4584]
n OEWX^}bv
Addr 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH Register Name Power Down Control Reset Control Clock & Format Control Deem & Volume Control Lch IPGA Control Rch IPGA Control Lch OATT Control Rch OATT Control In/Out Source Control Clock Mode Control DIR Control DIT Control INT0 Mask INT1 Mask Receiver Status 0 Receiver Status 1 RX Channel Status Byte 0 RX Channel Status Byte 1 RX Channel Status Byte 2 RX Channel Status Byte 3 RX Channel Status Byte 4 TX Channel Status Byte 0 TX Channel Status Byte 1 TX Channel Status Byte 2 TX Channel Status Byte 3 TX Channel Status Byte 4 Burst Preamble Pc Byte 0 Burst Preamble Pc Byte 1 Burst Preamble Pd Byte 0 Burst Preamble Pd Byte 1 D7 0 0 0 MSDTO IPGL7 IPGR7 ATTL7 ATTR7 0 OCKS1 0 0 MAT0 MAT1 AUTO 0 CR7 CR15 CR23 CR31 CR39 CT7 CT15 CT23 CT31 CT39 PC7 PC15 PD7 PD15 D6 0 0 0 SMUTE IPGL6 IPGR6 ATTL6 ATTR6 0 OCKS0 CS12 0 MDTS0 MDTS1 DTSCD 0 CR6 CR14 CR22 CR30 CR38 CT6 CT14 CT22 CT30 CT38 PC6 PC14 PD6 PD14 D5 0 0 0 DZFE IPGL5 IPGR5 ATTL5 ATTR5 DAC1 ICKS1 OPS1 TX3E MAN0 MAN1 AUDION 0 CR5 CR13 CR21 CR29 CR37 CT5 CT13 CT21 CT29 CT37 PC5 PC13 PD5 PD13 D4 TEST 0 DIF2 ZCEI IPGL4 IPGR4 ATTL4 ATTR4 DAC0 ICKS0 OPS0 TX2E MV0 MV1 VDIR 0 CR4 CR12 CR20 CR28 CR36 CT4 CT12 CT20 CT28 CT36 PC4 PC12 PD4 PD12 D3 PWDITN 0 DIF1 ZTM1 IPGL3 IPGR3 ATTL3 ATTR3 PCM1 CM1 IPS1 TX1E MPE0 MPE1 PEM FS3 CR3 CR11 CR19 CR27 CR35 CT3 CT11 CT19 CT27 CT35 PC3 PC11 PD3 PD11 D2 PWVRN 0 DIF0 ZTM0 IPGL2 IPGR2 ATTL2 ATTR2 PCM0 CM0 IPS0 UDIT MUL0 MUL1 UNLOCK FS2 CR2 CR10 CR18 CR26 CR34 CT2 CT10 CT18 CT26 CT34 PC2 PC10 PD2 PD10 D1 PWADN RSTADN DFS1 DEM1 IPGL1 IPGR1 ATTL1 ATTR1 DIT1 XTL1 EFH1 VDIT MPR0 MPR1 PAR FS1 CR1 CR9 CR17 CR25 CR33 CT1 CT9 CT17 CT25 CT33 PC1 PC9 PD1 PD9 D0 PWDAN RSTDAN DFS0 DEM0 IPGL0 IPGR0 ATTL0 ATTR0 DIT0 XTL0 EFH0 TCH MFS0 MFS1 FS FS0 CR0 CR8 CR16 CR24 CR32 CT0 CT8 CT16 CT24 CT32 PC0 PC8 PD0 PD8
PDN = "L" resets the registers to their default values.
n OEWX^*Y'eZI'*O"_ "dOE"S"uZ"TM*A PDNs" "L"(c)c "H"E1/2*e*I*AEIV*[P"XAfoCX--*aA*B
IZ*AR"g**[OEWX^I*Su'lA AK4584ISZbg*o`OA**B (1) N*bN*[hAE"u*o--ItH*[}bg"TMI*Y'e*s*B (2) RSTADN, RSTDAN "1"EASZbg*o`O*oe*e*B Control Register (01H)ZQ*AEA*B Reset (3) ADC*o--IAEAC*o--IISZbg*o`O*oe*eUASO*"A~...*[gA*B D U1/2*A}X^*[hZI LRCKAE BICK*o--IIZu"g*"af...*[eB--*eeA"\* eU**B N*bN*Y'eOEWX^I*I*XI*A RSTADNAE RSTDAN "0"EA(c)cZA*sA*BISO*A ADC*o--IAE DAC*o--IISO*"A~...*[gA*BU1/2*A}X^*[hZI BICK*o--IIZu"g*"af...*[eB LRCKAE --*eeA"\* eU**B
MS0118-J-01 - 37 -
2001/11
ASAHI KASEI
[AK4584]
n *U*x*a-3/4
Addr 00H Register Name Power Down Control R/W Default D7 0 RD 0 D6 0 RD 0 D5 0 RD 0 D4 TEST R/W 1 D3 PWDITN R/W 1 D2 PWVRN R/W 1 D1 PWADN R/W 1 D0 PWDAN R/W 1
PWDAN: DAC Power Down 0: Power down 1: Power up "0"ADAC*"IYp**[_E"eU**BIZ*ALOUT/ROUTI`|*AE Hi-ZEEe*A*o--I ATTae 'U"FFH"EEeU**B'A*AR"g**[OEWX^I"a--eI*SueUn*BU1/2*AR"g**[ OEWX^OI*`*YaA"\A**Bp**[_E"*oeZI*o--I ATTR"g**[OEWX^I*Y 'e'l (06H, 07H)UAtF*[hC"U**B*Y'eZyN*oeZImCY"-*IA"\* eIASO*" A~...*[gA*B PWADN: ADC Power Down 0: Power down 1: Power up "0"AADC*"IYp**[_E"eU**BIZ*ASDTOI`|*AE "L"EEe*A"u--I GAae'U "00H" P EEeU**B'A*AR"g**[OEWX^I"a--eI*SueUn*BU1/2*AR"g**[OEWX ^OI*`*YaA"\A** B p**[_E"*oeZI"u--I PGAR"g**[OEWX^I*Y'e'l (04H, 05H)UAtF*[hC"U**B'A*A*A*I 516LRCKTCNI"0"*o--IeU**B PWVRN: VREF Power Down 0: Power down 1: Power up "0"AfoCX`S`Ip**[_E"eU**Bp**[_E"ZIR"g**[OEWX^I"a--eI* SueUn*BU1/2*AR"g**[OEWX^OI*`*YaA"\A**B PWDITN: DIT Power Down 0: Power down 1: Power up "0"ADIT*"IYp**[_E"eU**B*]AA*ATX1, TX2OoCtF*[Y*M*I*o--IIA U**A TX3(c)cIoCtF*[Y*M*I*o--IeUn*Bp**[_E"ZIR"g**[OEWX ^I"a--eI*SueUn*BU1/2*AR"g**[OEWX^OI*`*YaA"\A**B TEST: TEST bit "1"EOEA'eA**BIrbgOI*`*UEA*B
MS0118-J-01 - 38 -
2001/11
ASAHI KASEI
[AK4584]
Addr 01H
Register Name Reset Control R/W Default
D7 0 RD 0
D6 0 RD 0
D5 0 RD 0
D4 0 RD 0
D3 0 RD 0
D2 0 RD 0
D1 RSTADN R/W 0
D0 RSTDAN R/W 0
RSTDAN: DAC Reset 0: Reset 1: Normal Operation "0"ADAC*"SZbg*o`OEEeU**BIZ*A LOUT/ROUTI`|*AE VCOMOExEEe*A*o--I ATTae'U "FFH"EEeU**B'A*AR"g**[OEWX^I"a--eI*SueUn*BU1/2*AR "g**[OEWX^OI*`*YaA"\A**BSZbg*oeZI*o--I ATTR"g**[OEWX^ I*Y'e'l (06H, 07H)UAtF*[hC"U**B*Y'eZyN*oeZImCY"-*IA"\* eIA SO*"A~...*[gA*B RSTADN: ADC Reset 0: Reset 1: Normal Operation "0"AADC*"IYSZbg*o`OEEeU** B IZ*A SDTOI`|*AE "L"EEe* A "u--IPGAae'U "00H" EEeU**B'A*AR"g**[OEWX^I"a--eI*SueUn*BU1/2*AR"g**[OEWX ^OI*`*YaA"\A** B p**[_E"*oeZI"u--I PGAR"g**[OEWX^I*Y'e'l (04H, 05H)UAtF*[hC"U**B'A*A*A*I 516LRCKTCNI"0"*o--IeU**B
Addr 02H
Register Name Clock and Format Control R/W Default
D7 0 RD 0
D6 0 RD 0
D5 0 0 0
D4 DIF2 R/W 0
D3 DIF1 R/W 1
D2 DIF0 R/W 0
D1 DFS1 R/W 0
D0 DFS0 R/W 0
DFS1-0: Sampling Speed Control (see Table 6) *Su'lI"00"A**B DIF2-0: Audio Data Interface Modes (see Table 16) *Su'lI"010"(ADC, DACAEa24bit`Ol )A**B
MS0118-J-01 - 39 -
2001/11
ASAHI KASEI
[AK4584]
Addr 03H
Register Name Deem and Volume Control R/W Default
D7 MSDTO R/W 0
D6 SMUTE R/W 0
D5 DZFE R/W 0
D4 ZCEI R/W 1
D3 ZTM1 R/W 1
D2 ZTM0 R/W 0
D1 DEM1 R/W 0
D0 DEM0 R/W 1
DEM1-0: De-emphasis Response (see Table 21) *Su'lI"01"(OFF)A**B ZTM1-0: Zero Crossing Time-out Period Select (see Table 20) *Su'lI"10"(1024/fs)A**B ZCEI: ADC IPGA Zero Crossing Enable 0: Input PGA gain changes occur immediately 1: Input PGA gain changes occur only on zero-crossing or after timeout. *Su'lI"1"(Cl*[u )A**B DZFE: Data Zero Detect Enable 0: Disable 1: Enable [*OEY*o@"\I DZFErbg "0"E*eAEA-OEoEAU**BIZ*ADZFs"I*iE "L"A**B *Su'lI"0"(fBZ*[u)A**B SMUTE: DAC Input Soft Mute Control 0: Normal operation 1: DAC outputs soft-muted \tg~...*[gI*o--I ATTAEI"AE--E"(R)*i*AfBW^"IEZA*seU**B MSDTO: SDTO Mute Control 0: Disable 1: Enable MSDTOrbg "1"IZ*A SDTO*o--IE~...*[g(c)U**BIZ*A SDTO*o--II L"EEeU**B " *Su'lI"0"(fBZ*[u)A**B
Addr 04H 05H
Register Name Lch IPGA Control Rch IPGA Control R/W Default
D7 IPGL7 IPGR7 R/W 0
D6 IPGL6 IPGR6 R/W 1
D5 IPGL5 IPGR5 R/W 1
D4 IPGL4 IPGR4 R/W 1
D3 IPGL3 IPGR3 R/W 1
D2 IPGL2 IPGR2 R/W 1
D1 IPGL1 IPGR1 R/W 1
D0 IPGL0 IPGR0 R/W 1
IPGL/R7-0: ADC Input Gain Level (see Table 23) *Su'lI"7FH" (0dB)A**B 7FHEIR*[h*`*AE 128OExIfBW^ATT"(R)*iU**B ATTI"a*" 8032OExI SjAATTEEAAe*ASO*"128OExI^Z--*Of*[^ESe"-AceU**B ATT'lSOI`JU I 8032OExA\tg`JUU**B--a|I*A 127(c)c 126E*eAE*A"a*"I 8031(c)c 7775UAfsTC N-E "1"AOE*SU**B 127(c)c 0(Mute)UAEI 8031TCN182ms@fs=44.1kHz)(c)(c)eU ( **B PDNs" "L"Z "00H"E*Y'ee*APDNs" "H"A*Su'l "7FH"UA8031TCNAtF*[hC" U**B PWADNrbg ="0"Z "00H"E*Y'ee*A PWADNrbg ="1"AIZI*Y'e'lUAtF*[hC" U**B'A*A*A*I 516TCNI"0"*o--IeU**B RSTADNrbg ="0"Z "00H"E*Y'ee*ARSTADNrbg ="1"AIZI*Y'e'lUAtF*[hC" U**B'A*A*A*I 516TCNI"0"*o--IeU**B
MS0118-J-01 - 40 -
2001/11
ASAHI KASEI
[AK4584]
Data 255 - 165 164 163 162 : 130 129 128 127 126 125 : 112 111 110 : 96 95 94 : 80 79 78 : 64 63 62 : 48 47 46 : 32 31 30 : 16 15 14 : 5 4 3 2 1 0
"a*"'l (DATT) 8031 7775 7519 : 4191 3999 3871 : 2079 1983 1919 : 1023 975 943 : 495 471 455 : 231 219 211 : 99 93 89 : 33 30 28 : 10 8 6 4 2 0
Gain (dB) +18 +18 +17.5 +17 : +1.0 +0.5 0 0 -0.28 -0.57 : -5.65 -6.06 -6.34 : -11.74 -12.15 -12.43 : -17.90 -18.32 -18.61 : -24.20 -24.64 -24.94 : -30.82 -31.29 -31.61 : -38.18 -38.73 -39.11 : -47.73 -48.55 -49.15 : -58.10 -60.03 -62.53 -66.05 -72.07 MUTE
Step** (dB) 0.5 0.5 0.5 0.5 0.5 0.5 0.28 0.29 : 0.51 0.41 0.28 : 0.52 0.41 0.28 : 0.53 0.42 0.29 : 0.54 0.43 0.30 : 0.58 0.46 0.32 : 0.67 0.54 0.38 : 0.99 0.83 0.60 : 1.58 1.94 2.50 3.52 6.02
IPGA 0.5dB stepIAi*O{S...*[
IATT 128OExEIZ(R)A 8032OExISj A DATTE*IS**e* "a*" DATTI*Y'e'lI B SOI\tg`JU*e*B "a*"'l =2^m x (2 x l + 33) - 33 m: DataI*aE 3-bits l: DataIE4-bits
Table 23. IPGA Code Table
MS0118-J-01 - 41 -
2001/11
ASAHI KASEI
[AK4584]
Addr 06H 07H
Register Name Lch OATT Control Rch OATT Control R/W Default
D7 ATTL7 ATTR7 R/W 1
D6 ATTL6 ATTR6 R/W 1
D5 ATTL5 ATTR5 R/W 1
D4 ATTL4 ATTR4 R/W 1
D3 ATTL3 ATTR3 R/W 1
D2 ATTL2 ATTR2 R/W 1
D1 ATTL1 ATTR1 R/W 1
D0 ATTL0 ATTR0 R/W 1
ATTL/R7-0: DAC OATT Level (see Table 24) *Su'lI"FFH" (0dB)A**B ATTL/R7-0*Y'e'lSOI`JUI 7425OExA\tg`JUU**B FFH(0dB)(c)c 00H(MUTE)UAEI 7424/fs(168ms@fs=44.1kHz)(c)(c)eU**B PDNs" "L"E*eAE*AATTL/R7-0I FFHE*SueU**B PWDANrbg ="0"Z "FFH"E*Y'ee*A PWDANrbg ="1"AIZI*Y'e'lUAtF*[hC" U**B RSTDANrbg ="0"Z "FFH"E*Y'ee*ARSTDANrbg ="1"AIZI*Y'e'lUAtF*[hC" U**B fBW^Ael*[^@"\I\tg~...*[g@"\AEI"AE--E"(R)*iU**B ATTL/R7-0 Attenuation FFH 0dB FEH -0.5dB FDH -1.0dB FCH -1.5dB : : : : 02H -126.5dB 01H -127dB 00H MUTE (-) Table 24. OATT Code Table
MS0118-J-01 - 42 -
2001/11
ASAHI KASEI
[AK4584]
Addr 08H
Register Name In/Out Source Control R/W Default
D7 0 RD 0
D6 0 RD 0
D5 DAC1 R/W 0
D4 DAC0 R/W 0
D3 PCM1 R/W 0
D2 PCM0 R/W 0
D1 DIT1 R/W 0
D0 DIT0 R/W 0
DIT1-0:
Input Selector for DIT (see Table 10) *Su'lI"00"A**B"10"IZIX*[*o--I (TX1/2)AE"--lI*o--I"3/4ceU**B
PCM1-0: Input Selector for SDTO (see Table 25) *Su'lI"00"A**B PCM1 0 0 1 1 PCM0 Input Source 0 ADC 1 SDTI 0 DIR 1 N/A Table 25. Input Selector for SDTO
Default
DAC1-0: Input Selector for DAC (see Table 26) *Su'lI"00"A**B DAC1 0 0 1 1 DAC0 Input Source 0 ADC 1 SDTI 0 DIR 1 N/A Table 26. Input Selector for DAC
Default
Addr 09H
Register Name Clock Mode Control R/W Default
D7 OCKS1 R/W 0
D6 OCKS0 R/W 1
D5 ICKS1 R/W 0
D4 ICKS0 R/W 0
D3 CM1 R/W 0
D2 CM0 R/W 1
D1 XTL1 R/W 0
D0 XTL0 R/W 0
XTL1-0: X'tal Frequency Select (see Table 11) *Su'lI"00"A**B CM1-0: Master Clock Operation Mode Select (see Table 1) *Su'lI"01"A**B ICKS1-0: Master Clock Input Frequency Select at X'tal Mode (see Table 5) *Su'lI"00"A**B OCKS1-0: Master Clock Output Frequency Select at PLL Mode (see Table 2) *Su'lI"01"A**B
MS0118-J-01 - 43 -
2001/11
ASAHI KASEI
[AK4584]
Addr 0AH
Register Name DIR Control R/W Default
D7 0 RD 0
D6 CS12 R/W 0
D5 OPS1 R/W 0
D4 OPS0 R/W 0
D3 IPS1 R/W 0
D2 IPS0 R/W 0
D1 EFH1 R/W 0
D0 EFH0 R/W 1
EFH1-0: Interrupt 0 Pin Hold Count Select (Table 27) *Su'lI"01"A**B Table 27I LRCKI DIRI LRCKA*Az*[hZSOI 1/fsE"a--aU**B EFH1 0 0 1 1 EFH0 Hold Count 0 512LRCK 1 1024LRCK 0 2048LRCK 1 4096LRCK Table 27. Hold Count Select
Default
IPS1-0:
Input Recovery Data Select (see Table 8) *Su'lI"00"A**B
OPS1-0: Output Through Data Select for TX1/2 (see Table 9) *Su'lI"00"A**B CS12: Channel Status Select 0: Channel 1 1: Channel 2 C-bit, AUDION, PEM, FSE"1/2feelXe*[^X`I`U**B *Su'lI"0"A**B
MS0118-J-01 - 44 -
2001/11
ASAHI KASEI
[AK4584]
Addr 0BH
Register Name DIT Control R/W Default
D7 0 RD 0
D6 0 RD 0
D5 TX3E R/W 1
D4 TX2E R/W 1
D3 TX1E R/W 1
D2 UDIT R/W 1
D1 VDIT R/W 0
D0 TCH R/W 0
TCH: Channel Number Select for DIT 0: Don't care (bit20-23 = 0000) 1: Stereo (bit20-23 = 1000 : L channel, bit20-23 = 0100 : R channel) DIT*"Il"O* (C-bitI bit20-23)Z(c)"(R)*Y'eU**B*Su'lI "0"A**B R"V...*[}*[h (CT0rbg ="0")I*e**AAhOEX CT20-23rbgI*`*Y*sAA**B 17HI VDIT: V-bit Control for DIT 0: Valid 1: Invalid *Su'lI"0"A**B UDIT: U-bit Control for DIT 0: U-bit is fixed to "0". 1: Recovered U-bit is used for DIT. (Loop mode for U-bit) DIRA"*bNZ*A U-bitI "0"*o--IeU**B*Su'lI "1"A**B TX1E: TX1 Output Enable 0: Disable, TX1 outputs "L". 1: Enable *Su'lI"1"A**B TX2E: TX2 Output Enable 0: Disable, TX2 outputs "L". 1: Enable *Su'lI"1"A**B TX3E: TX3 Output Enable 0: Disable, TX3 outputs "L". 1: Enable *Su'lI"1"A**B
MS0118-J-01 - 45 -
2001/11
ASAHI KASEI
[AK4584]
Addr 0CH
Register Name INT0 Mask R/W Default
D7 MAT0 R/W 1
D6 MDTS0 R/W 1
D5 MAN0 R/W 1
D4 MV0 R/W 1
D3 MPE0 R/W 1
D2 MUL0 R/W 0
D1 MPR0 R/W 0
D0 MFS0 R/W 1
MFS0: Mask Enable for FS Bit 0: Mask disable 1: Mask enable MPR0: Mask Enable for PAR Bit 0: Mask disable 1: Mask enable MUL0: Mask Enable for UNLOCK Bit 0: Mask disable 1: Mask enable MPE0: Mask Enable for PEM Bit 0: Mask disable 1: Mask enable MV0: Mask Enable for VDIR Bit 0: Mask disable 1: Mask enable MAN0: Mask Enable for AUDION Bit 0: Mask disable 1: Mask enable MDTS0: Mask Enable for DTSCD Bit 0: Mask disable 1: Mask enable MAT0: Mask Enable for AUTO Bit 0: Mask disable 1: Mask enable
MS0118-J-01 - 46 -
2001/11
ASAHI KASEI
[AK4584]
Addr 0DH
Register Name INT1 Mask R/W Default
D7 MAT1 R/W 0
D6 MDTS1 R/W 0
D5 MAN1 R/W 0
D4 MV1 R/W 0
D3 MPE1 R/W 1
D2 MUL1 R/W 1
D1 MPR1 R/W 1
D0 MFS1 R/W 1
MFS1: Mask Enable for FS Bit 0: Mask disable 1: Mask enable MPR1: Mask Enable for PAR Bit 0: Mask disable 1: Mask enable MUL1: Mask Enable for UNLOCK Bit 0: Mask disable 1: Mask enable MPE1: Mask Enable for PEM Bit 0: Mask disable 1: Mask enable MV1: Mask Enable for VDIR Bit 0: Mask disable 1: Mask enable MAN1: Mask Enable for AUDION Bit 0: Mask disable 1: Mask enable MDTS1: Mask Enable for DTSCD Bit 0: Mask disable 1: Mask enable MAT1: Mask Enable for AUTO Bit 0: Mask disable 1: Mask enable
MS0118-J-01 - 47 -
2001/11
ASAHI KASEI
[AK4584]
Addr 0EH
Register Name Receiver Status 0 R/W Default
D7 AUTO RD 0
D6 DTSCD RD 0
D5 AUDION RD 0
D4 VDIR RD 0
D3 PEM RD 0
D2 UNLOCK RD 0
D1 PAR RD 0
D0 FS RD 0
FS: Sampling Frequency Status 0: No change 1: Change IrbgIAhOEX0FHI FS3-0rbgE*IOEY*oeeAE"1"EEeU**B 0EH"CY* AEEaee*ASZbgeU**B PAR: Parity Error or Bi-phase Error Status 0: No error 1: Error TutOE*["aApSeBG*[U1/2IoCtF*[YG*[OEY*oeeAE PARrbg "1"EE eU**B 0EH"CY*AEEaee*ASZbgeU**B UNLOCK: PLL Lock Status 0: Lock 1: Unlock 0EH"CY*nAa*ASZbgeUn*B PEM: Pre-emphasis Bit Output 0: OFF 1: ON IrbgIlXe*[^XG"R*[hA**eU**B 0EH"CY*nAa*ASZbgeUn*B VDIR: Validity Bit 0: Valid 1: Invalid 0EH"CY*nAa*ASZbgeUn*B AUDION: Audio Bit Output 0: Audio 1: Non audio IrbgIlXe*[^XG"R*[hA**eU**B 0EH"CY*nAa*ASZbgeUn*B DTSCD: DTS-CD Auto Detect 0: No detect 1: Detect 0EH"CY*nAa*ASZbgeUn*B AUTO: Non-PCM Auto Detect 0: No detect 1: Detect 0EH"CY*nAa*ASZbgeUn*B
MS0118-J-01 - 48 -
2001/11
ASAHI KASEI
[AK4584]
Addr 0FH
Register Name Receiver Status 1 R/W Default
D7 0 RD 0
D6 0 RD 0
D5 0 RD 0
D4 0 RD 0
D3 FS3 RD 0
D2 FS2 RD 0
D1 FS1 RD 0
D0 FS0 RD 0
FS3-0:
Sampling Frequency Detection (see Table 12) *Su'lI"0000"A**B
Addr 10H 11H 12H 13H 14H
Register Name RX Channel Status Byte 0 RX Channel Status Byte 1 RX Channel Status Byte 2 RX Channel Status Byte 3 RX Channel Status Byte 4 R/W Default
D7 CR7 CR15 CR23 CR31 CR39
D6 CR6 CR14 CR22 CR30 CR38
D5 CR5 CR13 CR21 CR29 CR37
D4 CR4 CR12 CR20 CR28 CR36
D3 CR3 CR11 CR19 CR27 CR35
D2 CR2 CR10 CR18 CR26 CR34
D1 CR1 CR9 CR17 CR25 CR33
D0 CR0 CR8 CR16 CR24 CR32
RD Not Initialized
CR39-0:
Receiver Channel Status Byte 4-0
Addr 15H 16H 17H 18H 19H
Register Name TX Channel Status Byte 0 TX Channel Status Byte 1 TX Channel Status Byte 2 TX Channel Status Byte 3 TX Channel Status Byte 4 R/W Default
D7 CT7 CT15 CT23 CT31 CT39
D6 CT6 CT14 CT22 CT30 CT38
D5 CT5 CT13 CT21 CT29 CT37
D4 CT4 CT12 CT20 CT28 CT36 R/W 0
D3 CT3 CT11 CT19 CT27 CT35
D2 CT2 CT10 CT18 CT26 CT34
D1 CT1 CT9 CT17 CT25 CT33
D0 CT0 CT8 CT16 CT24 CT32
CT39-0: Transmitter Channel Status Byte 4-0 R"V...*[}*[h (CT0rbg ="0")I*e**AT20-23rbgI*`*Y*sAA**B C
Addr 1AH 1BH 1CH 1DH
Register Name Burst Preamble Pc Byte 0 Burst Preamble Pc Byte 1 Burst Preamble Pd Byte 0 Burst Preamble Pd Byte 1 R/W Default
D7 PC7 PC15 PD7 PD15
D6 PC6 PC14 PD6 PD14
D5 PC5 PC13 PD5 PD13
D4 PC4 PC12 PD4 PD12
D3 PC3 PC11 PD3 PD11
D2 PC2 PC10 PD2 PD10
D1 PC1 PC9 PD1 PD9
D0 PC0 PC8 PD0 PD8
RD Not Initialized
PC15-0: PD15-0:
Burst Preamble Pc Byte 1-0 Burst Preamble Pd Byte 1-0
MS0118-J-01 - 49 -
2001/11
ASAHI KASEI
[AK4584]
VXe*YOEv Figure 18IVXe*U`--aA**Bi`I"IEnHAE`'e--aEAAI*]{*[h (AKD4584)ZQ*AEA*B [*OE* ] *E TVDD = 3.0V, }X^*[*[h XTALE = "H", DMCK = "L" ,
S/PDIF sources
10 Shield 0.1 13k 44 RX2 Shield 1 TEST2 2 RX3 43 TEST1 42 RX1 41 PVSS 40 R 39 PVDD 38 LIN
5.1
Analog 5V
10 5.1
0.1 37 RIN 36 VREF 35 AVDD 34 AVSS ROUT 33 LOUT 32 VCOM 31
MUTE MUTE
Shield
3 NC 4 RX4
DZF 30 0.1 M/S 29
2.2
PDN Control
5 PDN 6 INT0 7 INT1
AK4584
LRCK 28 BICK 27 SDTI 26 SDTO 25 MCKO2 24 XTI/MCKI MCKO1 23 DMCK
P
8 CDTI 9 CDTO 10 CCLK 11 CSN XTALE TEST3 DVDD TVDD DVSS XTO TX1 TX2 TX3
Audio DSP
12
13
14
15
16
17
18
19
20
21
22
0.1 0.1 C 10 10 C
'* :
S/PDIF out
Digital 3V
- *...*"-*UnHI 11.2896MHz (c)c 24.576MHzE`IU**BU1/2*A CI'lI*...**U"(R)ZqEE`U**B - AK4584I AGND, DGNDAEZu*OR"g**["TMIO"hI*A"z*uA*B - LOUT/ROUT--e--E**xi"(R)*e*e*I'1/4--nE'i*R"ueA*B - TEST1, TEST2, NCs"I RX*M*IJbvS"O-h(R)1/2EO"h (PVSS)E*U`A*B - v_E"s" (TEST1, 2)ESOIfBW^"u--Is"II*[v"EEA*B - Rs"EI 13k 1%I'i*R PVSSAEISOE*U`A B * Figure 18. Typical Connection Diagram
MS0118-J-01 - 50 -
2001/11
ASAHI KASEI
[AK4584]
1. O"hAE"dOEIfJbvS"O "dOEAEO"hIZaee*uEI*\*'*OA*B'E*i*A AVDD, DVDD, PVDDEIVXeIAi*O"dOE YU**B AVDD, DVDD, PVDD*E"dOEAYee*e*EI*A"dOE--*aV*[P"X*l|e*K--v I eUn*B TVDDISO*" ICAEI I/F--pI"dOEEIAVXeIfBW^"dOEYA*BAVSS, DVSS, PVSSIAi*OO"hE*U`A*BVXeIO"hIAi*OAEfBW^A*A"z *uPC{*[h*aI"dOEEAEeA*U`A*B*--e--EIfJbvS"OR"f"TIEex-"dOE s"I-E*U`A*B 2. Si*"d VREFs"AEAVSSI"d**Ai*O"u*o--IOE"W*Y'eU** 'E*i*A B VREFs"I AVDDE*U`*A AVSS AEISOE0.1FIZ~bNR"f"T*U`U**B VCOMIAi*O*M*IR""dAEAZgieU**B Is"EI*Zu"gmCY*oeZ*e1/2E 2.2F'o"xI"dR"f"TAE*A--nE.1FIZ~bNR"f 0 "T AVSSAEISOE*U`A*B"AE*AZ~bNR"f"TIs"EAe3/4AA*U`A *BVCOMs"(c)c"d--ZaeAAIUn*BfBW^*M**A"AEN*bNI*I'SiOIJbvS" O"e1/2*AVREFAE VCOMs"(c)cAe3/4--A*B 3. Ai*O"u--I Ai*O"u--IIV"OG"h"u--IEEAAe*A"u--I'i*RI 10k(typ)A**B"u--IOE"WI"a*"IR""d (-nAVDD/2)'*SE0.6 x VREF Vpp(typ)EEeU**B'E*i*A"u--I*M*IR"f"TA DCJbgU**B IZJbgItZu"g*"I fc=1/(2RC)A**B AK4584I AVSS(c)c AVDDUAI"d"u--I*eAEAU**B *o--IR*[hItH*[}bgI2'sR"vS*"gA**B DCItZbg (ADCZ(c)`II DCItZbgaSU )I"a ` I HPFAL"ZeU**B AK4584I 64fsAAi*O"u--IT"vS"OU**BfBW^tB^I*A 64fsI*(R)*""{*tI`Nae*oe -`jZ~aeE*aImCY`SA*oeZU**B AK4584I 64fs*tImCYOE*See1/2EA"FSAW" OtB^(RCtB^ )"a` AU**B 4. Ai*O*o--I Ai*O*o--IIV"OG"h*o--IEEAAe*A*o--IOE"WI"a*"IR""d (-nAVDD/2)'*SE0.6x VREF Vpp(typ)EEeU**B"u--IR*[hItH*[}bgI 2'sR"vS*"gA*A 7FFFFFH(@24bit)E`IAI *ItXP*[*A800000H(@24bit)E`IAI*ItXP*[*A 000000H(@24bit)AI LOUT/ROUTI--*`z 'lI 0V*o--IeU**B "a` I * (VF*[s"OmCY IXCbgLpV^tB^ (SCF) )I"a` AESO*" LPFAOE*SeU**B 5. XTIs"AE XTOs" (1) *...*"-*UZqZg--p*e*e*I*A XTIs"AEXTOs"E"K*OE'lI C*U`A*B CI'lI*...*"-*UZq EE`U* (typ. 10 40pF)*B (2) SO*"(c)cN*bNY*e*e*I*AXTOs"I*[v"EA XTIs"(c)c"u--IA*BDVDDE *aI"dI*M*I"u--IEA*BXTIs"E CMOSOEx"u--I*e*e**A XTALEs" "L"*A PDNs " "L"E*eZI*AXTIs" "L"EOEA'eA*BU1/2*A DVDDEI"dI*M*"u--I*eZEI*A ACJbvA XTIs"(c)cN*bNY*A 40%DVDDE*aI"dI*M*"u--IA*BI*e **ATALEs"*A X PDNs"E`I*e XTIs"I*-nI eUn*B (3) XTIs"*A XTOs"Zg--pEZEI*A XTOs"I*[v"EA*AXTIs" DVSSE*U`A*B
MS0118-J-01 - 51 -
2001/11
ASAHI KASEI
[AK4584]
pbP*[W
44pin LQFP (Unit: mm) 12.80 0.30 10.00 0 ~ 0.2
33 23
1.70max
34
22
12 44 1 11
12.80 0.30
0.80
10.00
0.37 0.10 0 ~ 10
0.17 0.05
0.15
0.60 0.20
n Material & Lead finish
Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy Cu Solder (Pb free) plate
MS0118-J-01 - 52 -
2001/11
ASAHI KASEI
[AK4584]
}*[L"O
AKM AK4584VQ XXXXXXX
1
XXXXXXX : Date Code Identifier (7 digits)
*d--vE'*OZ-*
*
* * *
* *
{ * *] { { } (R) * ... * (c) { ( ) * * * (c) xTM(R) ...TM (R)/ * / (c) (c) (c) / / (c) ] (c) /(c) (R) /*
MS0118-J-01 - 53 -
2001/11

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